Stochastic Logical Effort and Smart Monte Carlo for Timing Yield Estimation and Optimization

This paper presents novel techniques for timing yield optimization and for yield estimation in the presence of large statistical process variations in integrated circuits. The techniques are based on our generalization of the logical effort delay model to circuits with stochastic parameter variations. In the spirit of the standard logical effort formalism, the stochastic gate delay model we propose separates the characterization of statistical variability from the gate topology, type, size and loading information. This separation of concerns is very powerful and facilitates the two novel approaches presented in this paper. In the first approach, we perform analytical and/or qualitave reasoning about timing yield and “back of the envelope” timing yield optimization in the same way that the logical effort formalism enables in the absence of timing variations. In the second approach, we improve the accuracy and efficiency of sign-off timing yield estimation based on transistor-level Monte Carlo simulations. We make novel use of importance sampling and other variance reduction methods in conjunction with the stochastic logical effort approximation for this